Flash memory system

ABSTRACT

A memory system ( 10 ) comprising a non-volatile memory ( 18 ) having memory locations ( 38 ), and a controller ( 16 ) for writing data structures to and reading data structures from the memory. The system ( 10 ) is architecturally configured so that the locations ( 38 ) can be written to individually but are erasable only in blocks. The controller ( 16 ) forms one or more erasable units ( 39 ) which are each subdivided into cells ( 50 ) each consisting of a group of locations ( 38 ). The controller ( 16 ) writes data structures to and reads structures from each cell ( 50 ) on a per cell basis. The system ( 10 ) may comprise a controller ( 16 ) embedded in a FLASH memory card. Alternatively, the controller ( 16 ) may be embedded in, or implemented in, a host system such as a Personal Computer (PC).

FIELD OF THE INVENTION

The present invention relates to a non-volatile memory system for datastorage and retrieval, where the system comprises a memory having memorylocations which can be written to individually but which can only beerased in blocks of locations, and a controller for controlling accessto these memory locations; the present invention also relates to anon-volatile memory for use in such a non-volatile memory system and toa controller for controlling the non-volatile memory. In particular, theinvention relates to FLASH memory systems having defective memorylocations and controllers for FLASH memories.

BACKGROUND OF THE INVENTION AND RELEVANT PRIOR ART

FLASH EPROM (erasable programmable read only memory) devices arecommonly used in the electronics industry for non-volatile data storage.FLASH memory devices are architecturally configured to have locationswhich may be written to individually but may only be erased in groupscalled erasable blocks. This architectural configuration arises becausegroups of transistors in FLASH memory are linked by a common erase line.Thus, the size of an erasable block (the number of storage locations) isdetermined by the architecture of the device, which is established atthe design and manufacturing stage, and cannot be altered by the user.

One application of data storage is storing data structures generated by,for example, a Personal Computer (PC). A problem arises if FLASH memoryhaving defective memory locations is used to store data structuresbecause these defective memory locations cannot be used reliably fordata storage.

One solution to this problem of having defective locations in a memoryis for the FLASH controller to avoid using any erasable blockscontaining a defective location. However, if erasable blocks containingdefective locations are never used (marked as unusable by thecontroller) then there may be a great waste of usable memory storagespace (depending on the size of the erasable blocks and the number ofusable memory locations therein) leading to a low memory harvest (a lowratio of usable memory locations to total memory locations).

It is an object of the present invention to provide a non-volatilememory system which obviates or mitigates the above disadvantage.

It is an object of the present invention to provide a non-volatilememory system including a memory having locations that are not usablefor data storage, but where the memory can be used for efficient storageand retrieval of data structures.

SUMMARY OF THE INVENTION

According to a first aspect of the present invention there is provided amemory system for connection to a host, the system comprising:

a non-volatile memory having memory locations,

and a controller for writing data structures to and reading datastructures from the memory, the system being architecturally configuredso that the locations can be written to individually but can only beerased in blocks of locations;

the improvement being that the controller forms at least one erasableunit, where each erasable unit comprises at least one erasable block,and the controller subdivides each erasable unit into groups oflocations (where each group is herein called a cell) and the controllerwrites data structures to and reads data structures from each cell on aper cell basis.

By virtue of the present invention, the memory is re-configured intocells so that the controller may avoid using an individual cellcontaining a defect, rather than having to avoid using an erasable blockcontaining a defect. This has the effect of increasing the memoryharvest.

An erasable unit may consist of only one erasable block. Alternatively,an erasable unit may consist of a plurality of erasable blocks;conveniently, a binary multiple of erasable blocks.

It will be understood that an erasable block will typically be muchlarger than a cell.

Prior to or during connection to the host, the memory locations in eachcell are tested and if a defect is present in even one location in acell, then the controller identifies the entire cell as being unusable,otherwise the entire cell is identified as being usable for storing datastructures.

It will be understood that the term memory location can refer to asingle bit of memory storage; whereas, the term cell refers to a largeplurality of bits of memory storage, typically a cell may store 256bytes or 512 bytes.

It will be understood that locations that can be written to individuallymay be formed by a plurality of physical memory locations, for example,a row of physical memory, so that in this case an entire row is thesmallest unit of memory that can be written to individually.

The non-volatile memory may comprise a plurality of memory devices, oronly a single memory device. The controller is, preferably, in the formof a master controller having a sub-controller incorporated into the oreach memory device. Alternatively, the controller is in the form of asingle controller which controls the or each memory device.

Preferably, the controller designates at least one of the usable cellsin each erasable unit as being reserved whereby there are unusable cellscontaining defects, reserved cells for storing control information, andusable cells for storing data received from the host.

Preferably, the reserved cells are used for storing address conversioninformation for converting an address from the host to an addresssuitable for accessing the memory.

Preferably, the address conversion is effected by having a plurality ofreserved cells linked together.

Preferably, each reserved cell is used to store pointer information forpointing to the next reserved cell until the last reserved cell isreached, which points to an address in the memory storing the addresssuitable for accessing the memory.

Preferably, reserved cells are configured to have a plurality ofentries, where each entry stores a plurality of fields, whereby a fieldstored in one entry is used to point to a field stored in another entryand only the most recently written field stored in an entry isconsidered to be valid.

According to a second aspect of the present invention there is provideda controller for use with a non-volatile memory having locations thatcan be written to individually but can only be erased in blocks oflocations, where, in use, the controller forms at least one erasableunit, where each erasable unit comprises at least one erasable block,and the controller subdivides each erasable unit into cells and readsdata structures from and writes data structures to the cells on a percell basis.

The term data structure is used to include all data stored in thememory. Thus, the term data structures includes read/write blocks (thatis, blocks of data which are transferred between a PC and the memory)and also control information (that is, information which is generatedby, for example, the memory controller).

According to a third aspect of the present invention there is provided anon-volatile memory for use with a controller, the memory havinglocations that can be written to individually but can only be erased inblocks of locations, the non-volatile memory being configured so that atleast one erasable unit is formed, where each erasable unit comprises atleast one erasable block, and each erasable unit is subdivided intogroups of memory locations called cells, so that data structures arewritten to and read from the cells by the controller on a per cellbasis.

The non-volatile memory may be configured by having each cell in eacherasable unit tested and the results of the test for each unit writtento a set of locations forming a header within that unit, so that eachunit has a header containing header information.

Alternatively, in an erasable unit comprising a plurality of blocks,each cell in each erasable block may be tested and the results of thetest for each erasable block written to a header within that block. Thecontroller may read the header information from each of a plurality oferasable blocks and concatenate the header information and store theconcatenated header information in a single header in an erasable unitcomprising the plurality of blocks which were read.

Preferably, at least one cell in each erasable unit is designated asbeing reserved for storing control information.

Preferably, a plurality of reserved (control) cells are linked togetherto form a hierarchy of cells for effecting address conversion, anddifferent levels in the hierarchy of cells are addressed by differentbits from a logical address supplied by a host, so that the lowest cellin the hierarchy provides either the actual physical address required orpointer information for pointing to another hierarchy of cells.

BRIEF DESCRIPTION OF THE DRAWINGS

These and other aspects of the present invention will be apparent fromthe following specific description, given by way of example, withreference to the accompanying drawings, in which:

FIG. 1 shows a block diagram of a memory system having a FLASH memory,according to one embodiment of the present invention;

FIG. 2 shows different configurations of defects which may occur in oneof the erasable blocks of the FLASH memory of FIG. 1;

FIG. 3A shows the erasable block of FIG. 2 subdivided into cells to forman erasable unit;

FIG. 3B shows an erasable unit comprising eight of the FIG. 2 erasableblocks;

FIG. 4 shows the erasable unit of FIG. 3A having five data structuresstored therein;

FIG. 5 illustrates how part of a cell map is constructed for theerasable unit of FIG. 3A;

FIG. 6A shows the format of a typical cell map;

FIG. 6B illustrates part of the cell map of FIG. 6A resulting from FIG.5;

FIG. 7 shows the format of a physical address for accessing the memoryof FIG. 1;

FIG. 8 shows a portion of FIG. 7 in more detail;

FIG. 9 shows the hierarchy of addressing used for converting logicaladdresses to physical addresses for the system of FIG. 1;

FIG. 10 shows a part of FIG. 9 in greater detail;

FIG. 11 shows the chain structure of the hierarchy of addressing of FIG.9, in the form of a secondary block address table;

FIG. 12 illustrates the table of FIG. 11 as stored in a control cell;

FIG. 13 shows the allocation of control cells in an erasable unit aftererasure of that unit;

FIG. 14 shows the format of an erasable unit physical address;

FIG. 15 shows an erasable unit having additional storage; and

FIG. 16 shows the hierarchy of layers within a host system in analternative embodiment of the present invention, where the controller isimplemented as a system software layer.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIG. 1 shows a memory system 10 connected to a Personal Computer 12 by astandard PC interface 14. The system 10 has a controller 16 connected toFLASH memory 18 for storing data structures. These data structures maybe generated by the PC 12 (read/write blocks) or by the controller 16(control information). The controller 16 manages transfer of datastructures between the PC 12 and the FLASH memory 18.

The controller 16 has PC interface hardware 20 connected to the PCinterface 14. The PC interface hardware 20 is connected to memoryinterface hardware 22 via data bus 24 and also control bus 26. A buffermemory 28 is also connected to the data bus 24 to provide temporarystorage of data which is to be written to the FLASH memory 18. Amicroprocessor 29 is embedded in the controller 16. The microprocessor29 communicates with PC interface firmware resident in non-volatilememory 30 and controller management firmware also resident innon-volatile memory 32 (shown separately for clarity) via the controlbus 26 and using volatile memory 33. The memory interface hardware 22communicates with the FLASH memory 18 via a second data bus 34.

The FLASH memory 18 is, typically, a 16 MBit memory architecturallyconfigured to have thirty-two erasable blocks (one of which is shown byway of example as block 36 in FIG. 2), each erasable block 36 havingmemory locations for storing 64 Kbytes.

The or each erasable block 36 is byte addressable and has 65536byte-wide memory locations 38, some of which, typically, are defective.By way of example, FIG. 2 shows a group of approximately tennon-defective locations 38 in the top left hand corner of block 36 anddifferent configurations of defective locations, such as point .40 (i.e.a simple single defective location), cluster 42, repeating cluster 44,row 46 and column 48 defects. For clarity, the size of the locations 38have been enlarged relative to the erasable block 36.

Access to the memory 18 always requires a physical address (whichaddresses a physical memory location); therefore, a logical address(such as that received by the controller 16 from the PC 12) must betranslated to a physical address to locate the data structure as storedin the physical device (memory 18).

All read/write blocks are written to and read from memory 18 as a serialblock transfer operation with a word size of one byte (eight bits).

In accordance with the present invention, the controller 16 creates anerasable unit 39 which may comprise one or more erasable blocks 36. Inone embodiment, as shown in FIG. 3A, the erasable unit 39 consists ofone erasable block 36. In other embodiments, an erasable unit 39 maycomprise a plurality of erasable blocks 36, for example, a binarymultiple of erasable blocks 36 which are sequentially located in memory18, as shown in FIG. 3B where an erasable unit 39 comprises eighterasable blocks 36.

The controller 16 ensures that each erasable unit 39 is independent ofall other erasable units 39 by ensuring that data structures stored inone erasable unit 39 do not overlap into another erasable unit 39.

Prior to incorporating the FLASH memory 18 into the memory system 10,the memory locations 38 are tested and the physical addresses of allfaulty locations are stored in a header near the start (lowest physicaladdress) of each erasable unit 39. The header is a sequence of m memorylocations, the first location of which is near to the start of anerasable unit. Thus, each erasable unit 39 contains the physicaladdresses of all of the defective locations, such as 40, 42, 44, 46, 48in that erasable unit 39. This means that m (non-defective) memorylocations are not available for storing data sent by the PC 12, butthese m locations are not necessarily the first m (or even consecutive)physical addresses in an erasable block, because the locations may bearranged in columns.

Referring to FIG. 3A and FIG. 2, the controller 16 forms an erasableunit 39 by subdividing each erasable block 36 into groups ofneighbouring memory locations 38: these groups of neighbouring memorylocations 38 are herein called cells 50. No physical subdivision of thememory actually occurs. The controller 16 merely considers each erasableunit 39 as being comprised of a certain number of cells, where each cellis a group of adjacent memory locations.

To minimise the storage space required the cells are preferablyidentical in size. Variable sized cells may be used, but would be muchmore complex.

Each cell 50 contains 512 addressable memory locations 38, each memorylocation 38 being one byte wide. The locations are arranged within acell 50 as sixteen columns and thirty-two rows.

The controller 16 generates a cell map for each erasable unit 39, wherethe cell map stores the locations (physical addresses) of defectivecells (that is, cells having at least one defective location) in theunit 39. The controller 16 is designed for a particular memoryarchitecture (erasable block size and erasable unit size) so that thecell map corresponds to the grid array of locations in the erasable unit39. The controller 16 then stores the cell map as header information inthe header 52 of the corresponding erasable unit 39.

The cell map is generated by a test unit (not shown) and written to theheader 52 during the manufacturing test process for the FLASH memory 18,but may be updated by the controller 16 if failures occur during theoperating life of the device.

The controller 16 controls erasure of an erasable unit 39, and prior toerasure the associated cell map is written to the erasable block buffermemory 28 and written back to the erasable unit 39 after erasure iscomplete. A back-up copy of the cell map is also written to the nexterasable unit 39 for security purposes.

If a cell 50 contains one or more defective memory locations, then thecell 50 is marked as defective (in the cell map), as will described inmore detail below.

Each erasable unit 39 will be able to store data in cells 50 which areavailable for data storage (usable cells 51) but not in defective cells54 or in cells allocated (reserved) for storing control information(control cells 56), such as the header 52. Thus the logical capacity(the number of addressable locations available for data storage) of eacherasable unit 39 will be smaller than the physical capacity (the totalnumber of addressable memory locations 38) of each erasable unit 39.

Read/write blocks having identical logical lengths (that is, the samenumber of data bits) may occupy different amounts of physical memoryspace (a different number of memory locations 38) because of defectivecells 54 and control cells 56 (both of which are skipped when read/writeblocks are read or written). This is illustrated in FIG. 4.

In FIG. 4, five read/write blocks 60 a, b, c, d and q are stored in theerasable unit 39. Read/write blocks are usually stored contiguously inone or more rows of an erasable unit 39; for example, a first read/writeblock may finish at row 1 column 4 of a usable cell 51, and the nextread/write block will normally start at row 1 column 5 of the sameusable cell 51. An entire row in an erasable unit 39 (frequentlyspanning many usable cells 51) is filled with read/write blocks beforethe next row is used. Read/write blocks are therefore intended to becontiguous through rows of the locations in the erasable unit 39 andindependent of the cells 50. This is the way that 60 a, 60 b, 60 c, and60 d are stored. The starting location of 60 b is at the addressimmediately after the address of the last location of 60 a, the startinglocation of 60 c is immediately after the address of the last locationof 60 b, and so on.

However, to illustrate the effect of having many defective cells inclose proximity, read/write block 60 q is shown located near to thebottom of the erasable unit 39 (because there are more defective cellsnear the bottom of unit 39 in FIG. 4).

In the absence of defective cells 54 and control cells 56, read/writeblocks would be located at contiguous sequential addresses, filled on arow by row basis, within a single erasable unit 39. Read/write blocks 60b, 60 d, and 60 q have identical logical lengths. As can be seen fromFIG. 4, read/write blocks 60 can start at any column location of any rowwithin a cell 50; and, similarly, may finish at any column location ofany row within a cell 50. There is no requirement to start at aparticular row or column, or to finish at a particular row or column.

Read/write block 60 q is spread out over a much larger area of memorythan block 60 d, because twenty defective cells 54 are skipped by block60 q; whereas, only one defective cell 54 (and the one control cell 56)is skipped by block 60 d.

Each read/write block 60 has a header portion 62 and a data portion 64.The header portion 62 typically occupies twelve bytes of memory 18 andincludes: a flag to indicate whether the data in the data portion 64 isvalid; a logical block address for the read/write block; errorcorrecting codes (ECC) for protecting the data in the header portion 62;a code to indicate the type of data stored (for example, compressed,uncompressed, protected, and such like); and the physical address of thenext read/write block 60.

The data portion 64 contains the data which is stored. The length of thedata portion 64 is determined by the system 10. An error correcting codemay be added to the data by the controller 16. Read/write blocks 60received from the PC 12 have a fixed size which is determined by the PCinterface firmware 30.

It will be appreciated that the logical capacity of each erasable unit39 is variable and depends on the number of defective cells 54 and thenumber of control cells 56.

When a read/write block 60 is to be written to FLASH memory 18 then thecontroller 16 determines a suitable starting address for the block 60.The choice of starting address depends on the particular algorithmimplemented by the controller 16. For example, the controller 16 mayfill an entire row before incrementing to the next row: alternatively,the controller may fill an entire column before incrementing to the nextcolumn. The choice of algorithm used may depend on the architecture andcharacteristics of the memory device 18.

In this embodiment entire rows are filled first. That is, the lowestusable row address is used as the starting address and an entire row isfilled (by incrementing the column address) before the row address isincremented. Thus, the controller 16 searches the cell map for thelowest usable row address.

The controller then determines the number of usable cells 51 availablefor storing the read/write block 60 before the first defective cell 54is reached. The number of available memory locations can easily bedetermined from the number of usable cells 51 because there are sixteencolumns of locations in each cell 50, so the number of available memorylocations is equal to the number of usable cells 51 before the firstdefective cell 54 multiplied by sixteen.

If the entire block 60 can be stored without impinging on a defectivecell 54 (or a control cell 56) then the block 60 is stored. Examples ofthis are blocks 60 a and 60 c in FIG. 4.

If, however, only a portion of the block 60 can be stored before adefective cell 54 (or control cell 56) is reached then the portion thatcan be stored is transferred to the memory and stored, the transfer isthen halted while the controller 16 determines the location of the nextusable cell 51. The controller 16 then determines how much data can bestored between the next usable cell 51 and the defective cell 54 (orcontrol cell 56) immediately after the next usable cell 51. Thecontroller 16 then increments the address to be written to so that theaddress to be written to equals the first usable address, and theninitiates data transfer, and so on.

Alternatively, if the characteristics of the FLASH memory device do noteasily allow a new address for data transfer to be set up, for example,because it is configured for serial data transfer, a data transfer clockmay be generated by the controller 16 and applied to the memory devicewhilst no data is actually transferred. When internal access pointerswithin the memory device (driven by the clock signal) reach the nextusable address, the data transfer is re-initiated by the controller 16.

Thus, data transfer between the PC 12 and the FLASH memory 18 issegmented: each segment is stored in a set of sequential memorylocations. The length of each segment equals the number of contiguousavailable memory locations. A segment stops at the last address before adefective cell 54 (or control cell 56) is reached, and restarts (at thelowest usable address in the cell) when the next usable cell 51 isreached. Thus, the controller 16 determines the size of the segment tobe transferred. The effect of this segmented transfer when manydefective cells are present in the memory 18 is illustrated byread/write block 60 q.

A similar procedure is followed when data is to be read from FLASHmemory because defective cells (and control cells) must be skipped whenreading from memory. The controller 16 skips cells in the following way.When the last address in a segment is read, the controller 16 thenincrements the address to the first usable row address in the firstusable cell 51 immediately after the defective cell 54 or control cell56.

When a read/write block 60 is read and any ECC associated with thatread/write block 60 indicates that there are errors in the data readthen the controller 16 identifies the particular defective bits andmarks the usable cell or cells 51 containing these bits as defective andupdates the corresponding cell map. Alternatively, the controller 16 maymark all of the usable cell or cells 51 containing the read/write block60 as defective. In this way the controller 16 verifies the integrity ofeach usable cell 51 each time data is read from that usable cell 51.Thus, the controller 16 can identify new defects occurring in usablecells 51. In other embodiments a self-test procedure may be used. Oninitiation of the self-test procedure the controller 16 writes data toand then reads data from each usable cell 51 to determine whether any ofthe usable cells 51 contain defects.

The controller 16 uses a write pointer (as described in GB 2 291 991) topoint to the memory location to be written to next and an erase pointerto point to the erasable unit 39 to be erased next. Read/write blocksare always written to the location pointed to by the write pointer andthe controller 16 ensures that there is at least one erased erasableunit 39 between the write pointer and the erase pointer. The controlleralso uses a separate control cell write pointer to point to the nextmemory location to be written to with control information. The controlwrite pointer only points to locations within control cells 56.

FIG. 5 shows an erasable unit 39 having markings to illustrate how partof a cell map is constructed, in that the columns of cells are numberedfrom 0 to 15 and the rows are numbered from 0 to 7.

FIG. 6A shows the format of a typical cell map 70. Each cell map 70contains the address 71 of the erasable unit 39 to which the map 70relates; the number 72 of available control cells 56 in the erasableunit 39; the number 73 of usable cells 51 in the erasable unit 39; and astream of bits 74 representing the usable cells 51 in the block 36.

FIG. 6B illustrates how the stream of bits 74 is generated from FIG. 5.In FIG. 6B, the stream of bits 74 is shown in a grid patterncorresponding to the cell pattern of FIG. 5. In FIG. 6B, an additionalfirst column 75 and first row 76 are shown for clarity, but are notactually stored. The cell map 70, which includes the eight by sixteenarray of ones and zeros (the stream of bits 74), is stored in the header52 of each erasable unit 39. In embodiments where one erasable unit 39consists of a plurality of erasable blocks 36, a cell map may only bestored in the first erasable block of the erasable unit, but that cellmap is used for all of the erasable blocks in the erasable unit.Alternatively, a cell map for an erasable unit comprising a plurality oferasable blocks may overlap several erasable blocks, particularly ifeach erasable block consists of one row or a small number of rows ofmemory locations. The first column (Drow) 75 indicates the cell rownumber and the first row 76 indicates the cell column number (as per thenotation in FIG. 5). Column 75 and row 76 are not stored in the header52. If a cell is usable then the number zero is inserted in the relevantrow and column; however, if a cell is unusable (for example, because itis a defective or a control cell) then the number one is inserted in therelevant row and column.

For added security, a copy of the cell map 70 for an erasable unit 39may be stored in the header of the following erasable unit 39. This isto ensure that if a location in the header 52 of an erasable unit 39fails, then the cell map 70 stored in that header 52 can be recoveredfrom the following header 52. Information in the cell map 70 isprotected by an ECC which is incorporated in the information stored inthe header 52.

The header 52 contains a cell map 70 for the associated erasable unit39, a cell map 70 for the preceding erasable unit 39, a uniqueidentification to enable the controller 16 to identify the header 52, awrite start flag, a write finish flag, a control cell start flag, acontrol cell finish flag, and either control cell header information orcontrol cell header pointer information.

The write start flag is asserted (set to the non-erased state) when aread/write block is written to the erasable unit 39 for the first timeafter erasure of the unit 39. The write finish flag is asserted when theerasable unit 39 is filled with read/write blocks.

The control cell start flag is asserted when control cells (other thanthe control cell containing the header 52) are first written to aftererasure of the erasable unit 39. The control cell finish flag isasserted when all control cells are written to.

The control cell header pointer is only needed if there is insufficientroom in a single control cell for the entire header information, inwhich case the control cell header information is stored in anothercontrol cell which is pointed to by the control cell pointer.

FIG. 7 shows the format of a physical address 80 for accessing (i.e.reading from and writing to) the FLASH memory 18. The physical address80 has a first field 82 representing an erasable unit 39. In thisembodiment, an erasable unit 39 is equal in size to an erasable block36. The physical address 80 also has a second field 84 containing anaddress within an erasable unit 39. The address in the second field 84is with respect to the total physical address space of the erasable unit39. The second field 84 is used to define the location of any datastructure within an erasable unit 39.

FIG. 8 shows the second field 84 in more detail. The second field 84comprises a cell row 92, a row 94, a cell column 96, and a column 98.The cell row 92 is the particular row of cells within an erasable unit39 which is to be accessed. The row 94 is the physical address of theparticular row of locations (within the cell row 92) which is to beaccessed. This row address is relative to the first row in the cell.Similarly, the cell column 96 is the particular column of cells withinan erasable unit 39 which is to be accessed, and the column 98 is thephysical address of the column of locations (within the cell column 96)which is to be accessed. The column address is relative to the firstcolumn in the cell.

The order of data structures stored in physical address space iscompletely independent of the logical block address (LBA) of each datastructure. The data structure corresponding to any particular logicalblock may be located anywhere in physical address space. The datastructure physical address (PBA) which is assigned to each LBA isdefined in a set of tables known as block address tables (BAT) which canbe accessed via a pointer tables (PT) tree structure, as illustrated inFIGS. 9 and 10.

A boot structure 100 is stored in a control cell 56 in the firsterasable unit 39 in the memory 18. Copies of the boot structure 100 arealso stored in the second and last erasable units 39 in the memory 18for security purposes. The control cell 56 used for storing the bootstructure 100 is selected by the controller 16 to be the first controlcell position immediately after the control cell containing the header52.

The boot structure 100 is the first data structure that the controller16 must locate each time the system is initialised (that is, each timethe system has power restored after having been switched off). Thereason that the boot structure 100 must be located first is that itcontains two fundamental pointers: a header pointer 102 and a blockaddress pointer 104. The header pointer 102 is used to point to a headeraddress table (HAT) for determining the address of each header 52 ineach erasable unit 39. The HAT pointed to is the highest level (or root)HAT. The block address pointer 104 is used to point to a block addresstable (BAT) for converting logical addresses received from the PC 12 tophysical addresses suitable for accessing the FLASH memory 18. The BATpointed to is the highest level (or root) BAT.

The boot structure 100 stores the following information:

1. a unique signature to aid identification by the controller 16;

2. a pointer which points to the header of the erasable unit in whichthe structure 100 is located;

3. the number of the highest accessible erasable unit 39 in the memory18;

4. the total number of columns in a cell 50;

5. the total number of rows in a cell 50;

6. the total number of columns of cells in an erasable unit (forexample, 16 for FIG. 3);

7. the total number of rows of cells in an erasable unit (for example, 8for FIG. 3);

8. the logical address of a control block (will be described below);

9. the length of read/write block currently being used in the system 10;

10. the length of any ECC used in the read/write blocks;

11. the block address pointer 104; and

12. the header address pointer 102.

The block address pointer 104 defines the physical address of thecontrol cell in which the highest level (also known as root) blockaddress table is located. Similarly, the header address pointer 102defines the physical address of the control cell in which the highestlevel (also known as root) header address table is located.

FIG. 10 shows a logical address 110 of a read/write block 60, theaddress comprising n+1 fields (representing levels), the nth field(representing the highest level, or root of the tree) 112 being the mostsignificant bits of the address 110 and the zero field (representing thelowest level, or leaf of the tree) 114 being the least significant bitsof the address 110.

For each of the header address pointer 102 and the block address pointer104, the boot structure 100 contains an address which points to the(physical) starting address of a single nth level address table pointertable 116. The controller 16 uses the value of the nth field 112 topoint to a single entry in the nth level pointer table 116. The singleentry pointed to in the nth pointer table 116 is used to point to one ofthe address table n−1th level pointer tables 118. The particular entryin the n−1th level table 118 which is pointed to is determined by then−1th field of the logical address. This multi-level pointing processcontinues until the zero field 114 is used to point to an entry in theaddress table 120 which contains the actual physical address to beaccessed. The number of levels required is defined by the number ofentries per table 116,118,120 and the total logical capacity of thememory 18.

It will be appreciated that the same type of multi-level tree structurecan be used to determine the physical address of a header 52 as fordetermining the physical address of a read/write block 60.

FIG. 9 illustrates a tree structure arrangement for both a header 52 anda read/write block 60. A header address tree 130 is used to determinethe physical address of a header 52, and a block address tree 132 isused to determine the physical address of a read/write block 60.

The zero level tables (corresponding to 120 in FIG. 10) pointed to bythe block address tree 132 are the block address tables (BAT) 136.Similarly, the header address tree 130 points to the header addresstables 138.

There are two types of block address tables 136: primary BATs (PBATs)and secondary BATs (SBATs). A PBAT may be paired with one specific SBAT.PBATs and SBATs may be located anywhere in physical address space,however, they are always stored in control cells 56.

Each erasable unit 39 has at least one header control cell formaintaining the addresses (in the form of control cell headers) of thePBATs and SBATs within the erasable unit 39. This header control cellmay also contain the header 52, depending on the size of the controlcells 56 being used. Each PBAT contains entries for a predeterminednumber of read/write blocks 60.

An entry in a PBAT may contain the physical address in memory which isto be accessed or it may contain a pointer to an entry in the associatedSBAT. Similarly, the SBAT may contain the physical address in memorywhich is to be accessed or it may contain a pointer to another entry inthe same SBAT. Thus an indirect addressing chain may be constructedwhich tracks the movements of a read/write block. This provides anindirect addressing mechanism which allows the BAT 136 to be updatedwhen a read/write block is rewritten to a different location in memory18.

FIG. 11 shows the chain structure of a secondary block address table(SBAT) 139. Each SBAT entry 140 has three SBAT fields 142. Each field142 can be written sequentially and independently. In the example shownin FIGS. 11 and 12, a read/write block 60 may be written (relocated)thirty-one times before the SBAT needs to be erased. The maximum chainlength (each link of the chain being an SBAT field 142) in FIG. 11 isfour fields 142.

The first time that an SBAT is required (sector version one) the newread/write block address is written to field 142 a. The next time thatthe read/write block 60 is written (relocated) corresponds to sectorversion two, and the new address is written to field 142 b, which ispointed to by field 142 c; thus, two fields (142 b and c) have to bewritten. The next time that the read/write block is written (relocated)the new address is written to field 142 d, which is pointed to by field142 e; again, two fields (142 d and e) have to be written. Thus, foreach entry 140, only the most recently written field is treated asvalid. This procedure is repeated until all of the fields have beenwritten, which occurs in FIG. 11 when sector version thirty-one iswritten. Another example is when the read/write data block is writtenfor the seventeenth time (sector version 17 in FIG. 11), in which casefields 142 f and 142 g are written.

When all of the fields have been written, the whole SBAT 139 thenrequires erasure before it can be used. It will be appreciated that, forthis structure, at most two fields have to be updated each time aread/write block 60 is relocated. The chain structure for an SBAT 139has the advantage that it allows easy reconfiguration of chains as thecontroller writes and re-writes data blocks, without producing longlinks of chains which might hinder the speed of operation of the memorysystem 10.

FIG. 13 shows an erasable unit 39 having the same defective cells 54 asFIGS. 3 to 5, plus a defective cell at row 2 column 1. Each control cell56 is located at the first usable cell 51 in each row. Each time anerasable unit 39 is erased, it must be initialised by reserving usablecells 51 for use as control cells 56 according to some predeterminedalgorithm.

The number of usable cells 51 available as control cells 56 in eacherasable unit 39 is defined by a parameter stored in the cell map 70.The value of this parameter cannot be less than the number of controlcells 56 necessary for allocating the boot structure 100 and the header52. In this embodiment, the control cells 56 are allocated to the firstusable cell 51 in each non-fully defective row of the erasable unit 39.

This limitation on the maximum number of control cells 56 that can beused arises because some FLASH memories are liable to disturbanceeffects caused by multiple separate write operations within the same rowof the memory device. To counteract this, the number of control cells 56which may be allocated in the same row is restricted.

In this embodiment, the maximum value of the parameter is equal to thetotal number of usable cells 51 divided by sixteen because there aresixteen columns of cells in each erasable unit 39, and there is therestriction that only one cell can lie in each row.

When control cells 56 are written to, only one row in the control cell56 is written to then the row is incremented and the next row in thecontrol cell is written to, and so on. In contrast, when usable cells 51are written to, entire rows across the erasable unit 39 are written tobefore the row is incremented. Control data consists principally ofshort fields of data which are written independently at different times.Therefore, the use of a restricted number of control cells in a row forstorage of control data, rather than the use of a data structure like aread/write block in usable cells, provides a means of limiting thenumber of separate write operations within the same row of the memorydevice.

These control cells 56 are used to store the block address tables (BAT)136, the pointer tables (PT) 116 and 118, the header address tables(HAT) 138, the header 52, and the boot structure 100.

Each control cell 56 has a header with a unique code to identify whetherit stores information relating to a BAT 136, a PT 116, a HAT 138, aheader 52, or a boot structure 100. The control cell header also has anobsolete flag to indicate whether the information stored within thecontrol cell header is valid or obsolete.

As explained above, the headers for all control cells 56 within anerasable unit 39 are stored together in a single header control cellwithin the unit 39, which may also contain the header 52 for the unit39.

Each PBAT 136 has a plurality of entries, each entry relating to aspecific read/write block logical address. Each PBAT 136 relates to aset of contiguous logical addresses. Separate independent PBAT's existto provide sufficient capacity for all logical read/write blocks in thedevice. Each PBAT entry has, for example, three address fields. When aPEAT entry is written for the first time after erasure, the physicaladdress of the read/write block is written to the first address field.When the same logical block is rewritten at some later time, the newphysical address is entered in the second address field and the firstfield is no longer valid. When the same logical block is again rewrittenat some later time, the third field is used to provide an indirectaddress (an address for an SBAT entry 140). The controller 16automatically considers the address in the highest (most recentlywritten) of the three address fields as the valid address and disregardsall addresses in lower fields.

Some control information must be retained in the memory 18 to allowcorrect initialisation of the system 10 when the system 10 is firstdetected by the PC 12. To be easily locatable, this information must bestored in a predetermined location. However, this control information isupdated periodically during normal operation of the memory system 10, somemory wear would result from repeated erasure of the predeterminedmemory location. To avoid this problem, the control information isstored as a control block having a predetermined logical address ratherthan a predetermined physical address. Thus, the control block isrewritten to different areas of memory each time it is updated, but canalways be accessed by the same logical address.

The logical address of the control block is close to the top of thelogical address space of the memory 18, and is not accessible by the PC12. The highest logical address available to the PC 12 is immediatelybelow the control block address. The position of the control block inphysical memory is determined using the block address tables.

Header address tables 138 are stored in control cells 56 using thefollowing format. The HATs 138 have one entry for each erasable unit 39in the memory 18. Only one HAT 138 is located in a control cell 56. EachHAT entry is 16 bytes wide, so successive HAT entries are located at 16byte boundaries in a control cell 56. Thus, a control cell 56 canaccommodate 32 entries.

The controller 16 translates a logical address to a physical address(where the format of the logical block address for the read/write block60 to be read/written is that of logical address 110) in the followingway.

The controller 16 uses the block address pointer 104 to locate thehighest (nth) level block address pointer table 116, and accesses thecorrect entry in this table 116 by using the value of the nth field 112of the read/write logical address.

This entry points to the next (n−1th level) block address pointer table118. The entry pointed to by the n−1th field of the read/write addressis then accessed. This procedure is repeated through the n levels of thetable 118 until an entry in a block address table 136 is pointed to.

If this block address table entry is a direct pointer to an address inmemory 18 then the controller 16 reads the erasable unit header 52 forthe erasable unit 39 in which the read/write block 60 is located. Thecontroller 16 then reads the cell map 70. The read/write block headerportion 62 is then read by the controller 16 to verify that the logicalblock address field of the read/write block header 62 matches thelogical address 110 of the read/write block 60.

Before a data transfer operation between the PC 12 or buffer memory 28and the memory 18 is initiated, the controller 16 reads the cell map 70from the erasable unit 39 being accessed to determine theusable/unusable status of all of the cells 50 spanned by the read/writeblock 60. During data transfer, the controller 16 monitors the datatransfer to detect boundaries between usable cells 51 and either controlcells 56 or defective cells 54. When a boundary is encountered thetransfer is halted to allow the new (continuation) address to be loaded.

In the event that the write pointer address is lost, perhaps due topower failure, the correct address for the write pointer can be obtainedby scanning data structures on the memory 18 until a partially writtenerasable unit 39 is found, that is, an erasable unit 39 having the writestart flag asserted and the write finish flag not asserted. This isperformed by reading the state of the flags in sequential erasable unitheaders 52.

When the correct erasable unit 39 is found, the unit 39 is scanned untilthe first location is found (in a usable cell 51) having erased memory.This is the location of the write pointer.

The erase pointer is found by scanning erasable units 36 beginning withthe location of the write pointer until the first erasable unit is foundwhich ought to be erased according to the particular erase schedulingalgorithm being implemented. Each unerased unit 39 is identified byreading the data structure header immediately following the erasableunit header 52.

FIG. 14 shows the format of a modified erasable unit physical address84b for use in a FLASH memory architecture having additional storage.FIG. 15 shows an erasable unit 39 of a FLASH memory having main storage150 and additional storage 152 in the form of a single column of bytes.The erasable unit physical address 84 b (FIG. 14) has an additionaladdress bit (the xcell bit) 154 which is used to indicate whether theaddress represents main (bit 154 set to zero) or additional (bit 154 setto one) memory space.

When the xcell bit 154 is set to zero, the address 84 b is used in thesame way as described above for address field 84. When the xcell bit 154is set to one, however, the xcell having the row address correspondingto columns 92 and 94 is accessed. When additional storage 152 is used,the cell map 70 contains an additional column which is used to indicatewhether the xcell for each row is defective or working. If multiplecolumns of xcells are used, then columns 96 and 98 may be used to accessthe correct column of additional storage.

In use, the controller 16 writes all data structures to memory 18 byproviding a physical address for the start location of the data and alength of the data segment to be written. In the case of a read/writeblock which spans one or more defective or control cells or whichoverlaps from one physical memory row to another, the data structure iswritten as a number of separate data segments. In the case of a controldata structure within a control cell 56, the data is written as one ormore data segments, each occupying one row or part of a row of thecontrol cell 56. The physical address of a control data structure iseither calculated by the controller 16 or is obtained by reading anothercontrol data structure.

The above embodiments relate to a controller 16 having a processorembedded within a FLASH memory card and the necessary firmware. However,the controller 16 may be embedded in a host system, such as the PC 12;alternatively, the controller 16 may be implemented as a system softwarelayer (using control algorithms) in a host system which uses linearmemory cards. FIG. 16 illustrates the hierarchy of layers 160 within ahost system and a linear FLASH memory 162 to which the host isconnected. In the system of FIG. 16, the cell maps 70 may be generatedby a host software driver.

It will be appreciated that the present invention has the advantage thatby using cells to store either control information or read/write blocks,an erasable block may store both control information and read/writeblocks. In addition, by using pointers within cells to point to othercells, it is easy to store and keep track of control information whichneeds to be updated constantly. Erasure of the erasable blocks is simplebecause any valid control cells can be identified and relocated simply.

Various modifications may be made to the above described embodimentwithin the scope of the present invention. For example, an erasableblock 36 may be larger or smaller than 64 Kbytes; likewise, a cell maybe larger or smaller than 512 bytes, for example, 256 bytes may bepreferred. The particular value chosen for the erasable unit size willdepend on the manufacturer's choice but is generally related to thearchitecture, technology and cell type of the memory device 18. Theparticular value of the cell size chosen will depend on the memoryharvest required: if a smaller cell size is used then a greater harvestis available but larger cell maps are required for each erasable unit asmore cells are used. Error correction codes may be implemented in theabove data structures to minimise the possibility of losing valuabledata. Variable length data structures may be stored and retrieved. Itwill be appreciated that in other embodiments, the size of the datastructures may be different to those described, for example, if a largeror smaller memory is used. In other embodiments, FLASH memory 18 maycomprise memory devices which contain a large number of erasable blocks,each of which may be a row (sector) of the memory device or a smallnumber of contiguous rows, typically sixteen. In this case, an erasableunit 39 managed by the controller 16 may comprise a plurality oferasable blocks. In other embodiments the word size may be greater orless than eight bits, for example, sixteen bits or sixty-four bits. Inother embodiments, a chain length longer than four may be used. In suchembodiments, long chains of SBAT entries may develop as a result ofmultiple relocation of a read/write block 60. In such cases, the chainmay be broken by updating the PBAT entry that points to the beginning ofthe SBAT chain so that a new SBAT is pointed to. In other embodiments,the control cells 56 may be allocated in a different manner, forexample, control cells 56 may be allocated to the last usable cells 51in each row of the erasable unit 39, to the first cell in every secondrow; or more than one control cell 56 per row may be allocated. In otherembodiments, the cell maps 70 may be constructed by the controller 16,rather than by a separate device (the test unit).

What is claimed is:
 1. In a memory system for connection to a host, the system comprising: a non-volatile memory having a plurality of memory locations, and a controller for writing data structures to and for reading data structures from the memory, the system being architecturally configured so that the locations can be written to individually but can only be erased in blocks of locations, the improvement comprising: the controller is adapted to form at least one erasable unit comprised of at least one erasable block, and to subdivide each erasable unit into an integral number of cells where each cell comprises a group of physically contiguous locations, and the controller is configured to: receive data structures from the host in segments having identical length; write data from said received host data structures to the memory in segments having variable lengths; read data structures from the memory in said segments having said identical length; and to nominate at least one said cell as unusable for storage of data from said received host data structures and the remainder of said cells as usable for storage of data from said received host data structures, and to prevent any said variable length segments from being written to said at least one unusable cell wherein at least one cell in each said erasable unit is designated as being reserved for storing control information and is therefore nominated as said at least one cell which is unusable for storage of data from said received host data structures wherein the at least one reserved cell is configured to have a plurality of entries comprising a secondary block address table (SBAT), and where each entry stores a plurality of fields, wherein a first field stored in a first entry is used to point to a second field stored in a second entry and only a most recently written field stored in an entry is considered to be valid and upon writes or relocations of a block a plurality of times, avoiding erasure of the SBAT each time such relocation occurs.
 2. A memory system according to claim 1, wherein the memory locations in each cell are tested and if a defect is present in a cell, then the entire cell is nominated as being unusable for storage of data structures, cells not being so identified being nominated as usable for storage of data structures.
 3. A memory system according to claim 1 wherein the nonvolatile memory comprises at least one memory device.
 4. A memory system according to claim 3, wherein the controller controls a sub-controller incorporated into each of the at least one memory devices.
 5. A memory system according to claim 3, wherein the controller is in the form of a single controller which controls the at least one memory device.
 6. A memory system according to claim 1, further comprising a plurality of said reserved cells, wherein a portion of the reserved cells are used for storing address conversion information for converting an address received from the host to an address suitable for accessing the memory.
 7. A memory system according to claim 6, wherein each reserved cell is used to store pointer information for pointing to the next reserved cell until the last reserved cell is reached, said last reserved cell pointing to an address in the memory storing the address suitable for accessing the memory.
 8. A memory system according to claim 1, wherein the controller is configured to effect logical to physical address conversion by having a plurality of cells linked together to form a first hierarchy of cells including different levels, said different levels in the first hierarchy of cells being addressed by different bits from a logical address supplied by the host, so that a lowest cell in the first hierarchy provides one of the actual physical address required and pointer information for pointing to a second hierarchy of cells.
 9. A memory system according to claim 8, where the first hierarchy of cells consists of cells which are reserved for storing control information.
 10. A controller for use with a non-volatile memory having a plurality of locations that can be written to individually but can only be erased in blocks of locations, the controller forming at least one erasable unit, each said erasable unit comprising at least one erasable block, subdividing each erasable unit into an integral number of cells, each cell comprising a group of physically contiguous memory locations, and the controller being configured to: receive data structures from the host in segments having identical length; write data from said received host data structures to the memory in segments having variable lengths; read data structures from the memory in said segments having variable lengths and forward said read data structures to the host in segments having said identical length; and to nominate at least one said cell as unusable for storage of data from said received host data structures and the remainder of said cells as usable for storage for data from said received host data structures, and to prevent any said variable length segments from being written to said at least one unusable cell wherein at least one cell in each said erasable unit is designated as being reserved for storing control information and is therefore nominated as said at least one cell which is unusable for storage of data from said received host data structures wherein the at least one reserved cell is are configured to have a plurality of entries comprising a secondary block address table (SBAT), and where each entry stores a plurality of fields, wherein a first field stored in a first entry is used to point to a second field stored in a second entry and only a most recently written field stored in an entry is considered to be valid and upon writes or relocations of a block a plurality of times, avoiding erasure of the SBAT each time such relocation occurs. 